Design and Analysis of a Power and Delay Optimized Radix -4 Approximate Subtractor

Abstract

Subtraction is a fundamental arithmetic operation used in arithmetic logic units (ALUs), digital signal processing, image processing, and machine learning applications. Conventional subtractor architectures provide exact computation but often incur high hardware complexity, power consumption, and propagation delay due to extensive borrow propagation. Although approximate computing has emerged as an effective approach for improving hardware efficiency in error-tolerant applications, most existing approximate subtractor designs are based on conventional Radix-2 architectures, offering limited reduction in the borrow critical path. To address this limitation, this work proposes accurate and approximate Radix-4 subtractor architectures that simplify the borrow-generation logic while preserving acceptable computational accuracy. The proposed approximation reduces logic depth, gate count, power consumption, and propagation delay by selectively modifying the borrow path. The architectures are implemented using Verilog HDL and implemented on tool FPGA synthesis analysis.Experimental results demonstrate that the proposed approximate Radix-4 subtractors achieve lower power consumption and delay than their accurate counterparts while maintaining a low error rate, making them suitable for error-resilient applications such as multimedia processing, image processing, and machine learning